Multi-chip package system

ABSTRACT

A multi-chip package system includes a signal transmission line commonly coupled to a plurality of semiconductor chips to transfer data to/from the semiconductor chips from/to outside; and a termination controller suitable for detecting a loading value of the signal transmission line and controlling a termination operation on the signal transmission line based on the loading value.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of Korean Patent Application No.10-2013-0040066, filed on Apr. 11, 2013, which is incorporated herein byreference in its entirety.

BACKGROUND

1. Field

Exemplary embodiments of the present invention relate to a semiconductordesign technology, and more particularly, to a multi-chip package systemincluding a plurality of semiconductor chips.

2. Description of the Related Art

In general, semiconductor devices including Double Data Rate SynchronousDRAM (DDR SDRAM) have developed in various directions to satisfy usersrequests. The development directions may include a package technology. Amulti-chip package has been recently proposed as a package technologyfor a semiconductor device. The multi-chip package includes a pluralityof semiconductor chips constructing a single chip, and a plurality ofmemory chips with a memory function may be used to increase a memorycapacity, or a plurality of memory chips with different functions may beused to improve desired performance. For reference, the multi-chippackage may be divided into a single-layer multi-chip package and amultilayer multi-chip package depending on configurations. Thesingle-layer multi-chip package includes a plurality of semiconductorchips arranged in parallel to each other on the same plane, for example,coplanar, and the multi-chip package includes a plurality ofsemiconductor chips stacked therein.

FIG. 1 is a block diagram for explaining a conventional multi-chippackage.

Referring to FIG. 1, the multi-chip package includes a plurality ofsemiconductor chips 110 and a controller 120 to control thesemiconductor chips 110. The plurality of semiconductor chips 110 andthe controller 120 are connected to each other through a signaltransmission line LL, and the controller 120 transmits a predeterminedsignal through the signal transmission line LL so as to control theplurality of semiconductor chip 110.

Meanwhile, recent semiconductor devices have been developed in such adirection as to store a larger amount of data and perform variousoperations at higher speed. Therefore, the number of semiconductor chips110 constructing a multi-chip package as described above has beengradually increased. When the number of semiconductor chips 110 isincreased, it may mean that loading of the signal transmission line LLconnected to the controller 120 is increased as much. Furthermore, whenthe loading of the signal transmission line LL is increased, it may meanthat a delay amount corresponding to the increased loading isadditionally reflected into a signal transmitted through the signaltransmission line LL. When the delay amount is significantly increased,the signal may not be transmitted at high speed.

SUMMARY

Various exemplary embodiments are directed to a multi-chip packagesystem capable of controlling a signal transmission state depending onthe state of a transmission line commonly connected to a plurality ofsemiconductor chips.

In accordance with an embodiment of the present invention, a multi-chippackage system includes a signal transmission line commonly coupled to aplurality of semiconductor chips to transfer data to/from thesemiconductor chips from/to outside; and a termination controllersuitable for detecting a loading value of the signal transmission lineand controlling a termination operation on the signal transmission linebased on the loading value.

In accordance with another embodiment of the present invention, amulti-chip package system includes a controller suitable for generatingan enable signal for controlling an enable operation for a plurality ofsemiconductor chips, a switching block suitable for coupling a signaltransmission line to a number of semiconductor chips wherein the numberof semiconductor chips to be coupled is determined in response to theenable signal, and a termination controller suitable for controlling atermination operation on the signal transmission line in response to theenable signal.

In accordance with yet another embodiment of the present invention, amulti-chip package includes a plurality of semiconductor chips coupledto a through-silicon via (TSV) for transmitting a predetermined signal.Each of the semiconductor chips includes a chip identification (ID)generator suitable for generating a chip ID of a correspondingsemiconductor chip, and a termination controller suitable forcontrolling a termination operation on the TSV in response to an outputsignal of the chip ID generator.

In accordance with still yet another embodiment of the presentinvention, a multi-chip package system includes a multi-chip packageincluding a plurality of semiconductor chips coupled to a TSV fortransmitting a predetermined signal, and a controller suitable forcontrolling a termination operation on the TSV in response to the numberof the plurality of semiconductor chips.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram for explaining a conventional multi-chippackage.

FIG. 2 is a block diagram for explaining a multi-chip package system inaccordance with an exemplary embodiment of the present invention.

FIG. 3 is a block diagram for explaining a multi-chip package system inaccordance with another exemplary embodiment of the present invention.

FIG. 4 is a block diagram for explaining a multi-chip package system inaccordance with another exemplary embodiment of the present invention.

FIG. 5 is a block diagram for explaining a multi-chip package system inaccordance with another exemplary embodiment of the present invention.

FIG. 6 is a block diagram for explaining a multi-chip package system inaccordance with another exemplary embodiment of the present invention.

DETAILED DESCRIPTION

Various exemplary embodiments will be described below in more detailwith reference to the accompanying drawings. The present invention may,however, be embodied in different forms and should not be construed aslimited to the embodiments set forth herein. Rather, these embodimentsare provided so that this disclosure will be thorough and complete, andwill fully convey the scope of the present invention to those skilled inthe art. Throughout the disclosure, reference numerals corresponddirectly to the like numbered parts in the various figures andembodiments of the present invention.

FIG. 2 is a block diagram for explaining a multi-chip package system inaccordance with an exemplary embodiment of the present invention.

Referring to FIG. 2, the multi-chip package system includes a pluralityof semiconductor chips 210, a controller 220, and a terminationcontroller 230.

The plurality of semiconductor chips 210 are controlled by thecontroller 220, and the plurality of semiconductor chips 210 and thecontroller 220 are commonly connected to a signal transmission line LL.The controller 220 is configured to transmit a predetermined signalthrough the signal transmission line LL so as to control the pluralityof semiconductor chips 210.

The termination controller 230 is configured to detect a loading valueof the signal transmission line LL to control a termination operationfor the signal transmission line LL. The termination controller 230includes a loading value detection unit 231 and a termination operationunit 232. The loading value detection unit 231 is configured to detect aloading value of the signal transmission line LL and output the detectedvalue as a detection signal DET, and the termination operation unit 232is configured to perform a termination operation on the signaltransmission line LL in response to the detection signal DET.

In this exemplary embodiment of the present invention, a swing width ofa signal transmitted through the signal transmission line LL may becontrolled through the termination operation. That is, nee the signaltransmitted through the signal transmission line LL on which thetermination operation has been performed has a small swing width, thesystem may perform high-speed operation. However, when the terminationoperation is performed, the signal transmission line LL is driven to apredetermined voltage level, and thus power consumption inevitablyincreases. In this exemplary embodiment of the present invention,whether or not to perform a termination operation may be controlleddepending on the loading value of the signal transmission line LL, whichmakes it possible to realize high-speed operation and low powerconsumption. In other words, when the loading value of the signaltransmission line LL is relatively small, a termination operation maynot be performed to reduce power consumption. When the loading value ofthe signal transmission line LL is relatively large, a terminationoperation may be performed for a high-speed operation.

FIG. 3 is a block diagram for explaining a multi-chip package system inaccordance with another exemplary embodiment of the present invention.

Referring to FIG. 3, the multi-chip package system includes a pluralityof semiconductor chips 310, 320, and 330, a controller 340, a switchingblock 350, and a termination controller 360.

The plurality of semiconductor chips 310, 320 and 330 are controlled bythe controller 340 as in FIG. 2. For the illustrative purpose, threesemiconductor chips, that is, first to third semiconductor chips 310,320, and 330 will be taken as an example.

The controller 340 is configured to generate first to third enablesignals EN1, EN2, and EN3 for controlling an enable operation for thefirst to third semiconductor chips 310, 320, and 330, respectively. Thefirst enable signal EN1 is a signal for enabling the first semiconductorchip 310. Although not illustrated, the first enable signal EN1 may beapplied to the first semiconductor chip 310 so as to control the enableoperation. The second and third enable signals EN2 and EN3 are signalsfor enabling the second and third semiconductor chips 320 and 330,respectively. Similarly, the second and third enable signals EN2 and EN3may be applied to the second and third semiconductor chips 320 and 330so as to control the enable operation.

The switching block 350 is configured to connect signal transmissionlines, corresponding to semiconductor chips which are enabled inresponse to the first to third enable signals EN1 EN2, and EN3, to onetransmission line and includes first to third switching units SW1, SW2and SW3. The first switching unit SW1 is configured to connect a firstsignal transmission line 111 corresponding to the first semiconductorchip 310 to a signal transmission line LL in response to the firstenable signal EN1, the second switching unit SW2 is configured toconnect a second signal transmission line 112 corresponding to thesecond semiconductor chip 320 to the first signal transmission line 111in response to the second enable signal EN2, and the third switchingunit SW3 is configured to connect a third signal transmission line LL3corresponding to the third semiconductor chip 330 to the second signaltransmission line LL2 in response to the third enable signal EN3. Forexample, when the first and second enable signals EN1 and EN2 areactivated, the controller 340 and the first and second semiconductorchips 310 and 320 are connected through the signal transmission linesLL, LL1, and LL2 that are formed to one transmission line.

The termination controller 360 serves to control a termination operationof the signal transmission line LL in response to the third enablesignal EN3, and includes an enable detection unit 361 and a terminationoperation unit 362. The enable detection unit 361 serves to detect thatthe third enable signal EN3 is activated and output a detection signalDET, and the termination operation unit 362 serves to perform atermination operation on the signal transmission line LL in response tothe detection signal DET.

The multi-chip package system of FIG. 3 may perform a terminationoperation, when the third enable signal EN is activated, that is, whenthe first to third enable signals EN1 to EN3 are activated to connectthe controller 340 and the first to third semiconductor chips 310 to 330through the signal transmission lines LL, LL1, LL2, and LL3 that areformed to one transmission line. Therefore the enable detection unit 361receives the third enable signal EN3 and detects whether the thirdenable signal EN3 is activated or not.

Hereafter, a simple circuit operation will be described.

First, when only the first enable signal EN1 is activated, thecontroller 340 and the first semiconductor chip 310 are connectedthrough the signal transmission lines LL and LL1 that are formed to onetransmission line. In the configuration of FIG. 3 that controls whetheror not to perform a termination operation in response to the thirdenable signal EN3, suppose that one transmission line made from thesignal transmission lines LL and LL1 connected in response to the firstenable signal EN1 has a relatively small loading value, for example, avalue less than a given value. A termination operation is not thereforeperformed on the signal transmission line LL or LL1 connected throughthe first enable signal EN1. As a result, while a signal is transmitted,power consumption by a termination operation does not occur.

Next, when the first to third enable signals EN1 to EN3 are activatedthe controller 340 and the first to third semiconductor chips 310 to 330are connected through one signal transmission line LL LL2, and LL3 Inthe configuration of FIG. 3 suppose that one transmission line made fromthe signal transmission line LL, LL1, LL2, and LL3 connected in responseto the first to third enable signals EN1 to EN3 has a relatively largeloading value, for example, a value equal to or more than a given value.Therefore, a termination operation is performed on one transmission linemade from the signal transmission line LL, LL1, LL2, and LL3 connectedin response to the first to third enable signals EN1 to EN3. As aresult, a signal is transmitted with a small swing by the terminationoperation.

The multi-chip package in accordance with the embodiment of the presentinvention may detect a loading value of one signal transmission linethrough which enabled semiconductor devices are connected to each other,and may control whether or not to perform a termination operationaccording to the detection result.

FIG. 4 is a block diagram for explaining a multi-chip package system inaccordance with another exemplary embodiment of the present invention.FIG. 4 illustrates a case in which three semiconductor chips 410, 420,and 430 are provided.

Referring to FIG. 4, the multi-chip package system includes first tothird semiconductor chips 410 to 430, and the first to thirdsemiconductor chips 410 to 430 are connected to a first through-siliconvia (TSV) TSV_LL for transmitting a predetermined signal and a secondTSV TSV_DET for transmitting a detection signal DET. For convenience ofdescription, the first semiconductor chip 410 will be taken as arepresentative example.

The first semiconductor chip 410 includes a transmitter TX and areceiver RX which are connected to the first TSV TSV_LL. Furthermore,the first semiconductor chip 410 includes a chip identification (ID)generator 411 and a termination controller 412.

The transmitter TX is configured to receive a signal transmitted to thefirst semiconductor chip 410 and transmit the received signal to thefirst TSV TSV_LL, and the receiver RX is configured to receive a signaltransmitted through the first TSV TSV_LL and transmit the receivedsignal to internal circuits.

The chip ID generator 411 serves to allocate a chip ID to the firstsemiconductor chip 410. In the configuration of FIG. 4 in which thefirst semiconductor chip 410 is disposed at the lowermost part and thethird semiconductor chip 430 is disposed at the uppermost part, the chipID generator 411 of the first semiconductor chip 410 allocates a chip IDcorresponding to ‘1’ to the first semiconductor chip 410, the chip IDgenerator of the second semiconductor chip 420 receives the chip IDcorresponding to ‘1’ and allocates a chip ID corresponding to ‘2’ to thesecond semiconductor chip 420, and the chip ID generator of the thirdsemiconductor chip 430 receives the chip ID corresponding to ‘2’ andallocates a chip ID corresponding to ‘3’ to the third semiconductor chip430.

The termination controller 412 is configured to control a terminationoperation for the first TSV TSV_LL in response to an output signal ofthe chip ID generator 411, and includes a chip ID detection unit 412_1and a termination operation unit 412_2. The chip ID detection unit 412_1is configured to compare the chip ID corresponding to ‘1’ to a givenchip ID and generate a detection signal DET, and the terminationoperation unit 412_2 is configured to perform a termination operation onthe first TSV TSV_LL in response to the detection signal DET. At thistime, the detection signal DET may be transmitted to all of the first tothird semiconductor chips 410 to 430 through the second TSV TSV_DET.

The multi-chip package in accordance with the embodiment of the presentinvention may compare a chip ID of a corresponding semiconductor chip toa given chip ID, and control whether or not to perform a terminationoperation according to the comparison result. The given chip ID mayinclude information indicating that a termination operation will beperformed when the number of stacked semiconductor chips becomes equalto or more than a predetermined number. Supposing that the given chip IDcorresponds to ‘3’, a termination operation is performed on the firstTSV TSV_LL when the number of stacked semiconductor chips is equal to ormore than three, and is not performed on the first TSV TSV_LL when thenumber of stacked semiconductor chips is less than three.

In the embodiment of FIG. 4, the given chip ID may be stored in the chipID detection unit of each of the first to third semiconductor chips.That is, whether or not to perform a termination operation is determinedinside the multi-chip package. In an embodiment of FIG. 5 which will bedescribed below, whether or not to perform a termination operation maybe determined outside the multi-chip package.

FIG. 5 is a block diagram for explaining a multi-chip package system inaccordance with another exemplary embodiment of the present invention.

Referring to FIG. 5, the multi-chip package system includes a controller510 and a multi-chip package 520.

The controller 510 controls the multi-chip package 520 using a commandCMD, an address ADD, data DATA and the like, and controls a terminationoperation for the multi-chip package 520 in response to ID informationINF_ID which will be described below. The multi-chip package 520includes a plurality of semiconductor chips 521 controlled by thecontroller 510, and the plurality of semiconductor chips 521 areconnected to a TSV TSV_LL for transmitting a predetermined signal to theplurality of semiconductor chips 521.

Meanwhile, the controller 510 controls a termination operation for thefirst TSV TSV_LL in response to the ID information INF_ID. At this time,the ID information INF_ID may include a chip ID described with referenceto FIG. 4. That is, each of the semiconductor chips 521 provided in themulti-chip package 520 counts a chip ID and allocates the counted chipID as a chip ID for identifying the corresponding semiconductor chip,and the ID information IF_ID may include a finally-counted chip ID.Then, the controller 510 compares the counted chip ID to a given chipID, and determines whether or not to perform a termination operation forthe first TSV TSV_LL depending on the comparison result.

FIG. 6 is a block diagram for explaining a multi-chip package system inaccordance with another exemplary embodiment of the present invention.The multi-chip package system of FIG. 6 is different from the multi-chippackage system of FIG. 5 only in that the position of the terminationoperation unit 610 is different. That is, the termination operation unit610 of FIG. 6 is disposed outside the controller 510, and disposed moreadjacent to the mufti-chip package 520 than the controller 510.

Referring to FIG. 6, the controller 510 generates a control signal CTRfor controlling a termination operation in response to ID informationINF_ID generated by the multi-chip package 520, and the terminationoperation unit 610 performs a termination operation on a TSV TSV_LLconnected to the multi-chip package 520 in response to the controlsignal CTR.

As seen from FIGS. 5 and 6, the multi-chip package system in accordancewith the exemplary embodiment of the present invention may detect IDinformation counted in the multi-chip package and control whether or notto perform a termination operation depending on the detection result.

As described above, the multi-chip package systems in accordance withthe embodiments of the present invention may determine whether or not toperform a termination operation depending on a loading value of a signaltransmission line. In another embodiment, the multi-chip package systemmay also determine whether or not to perform a termination operationaccording to an enable signal for connecting a signal transmission line.In another embodiment, the multi-chip package system may also determinewhether or not to perform a termination operation depending on chip IDinformation of a plurality of semiconductor chips connected through aTSV. As a result, the multi-chip package system in accordance with theembodiment of the present invention may efficiently control whether ornot to perform a termination operation, thereby acquiring a gain interms of operation speed or power consumption when a signal istransmitted.

In accordance with the embodiments of the present invention, since themulti-chip package system may control a termination operation dependingon a loading value of a signal transmission line, the multi-chip packagesystem may operate more efficiently in terms of operation speed or powerconsumption.

Although various embodiments have been described for illustrativepurposes, it will be apparent to those skilled in the art that variouschanges and modifications may be made without departing from the spiritand scope of the invention as defined in the following claims.

1-4. (canceled)
 5. A multi-chip package system comprising: a controllersuitable for generating an enable signal for controlling an enableoperation for a plurality of semiconductor chips; a switching blocksuitable for coupling a signal transmission line to a number ofsemiconductor chips, wherein the number of semiconductor chips to becoupled is determined in response to the enable signal; and atermination controller suitable for controlling a termination operationon the signal transmission line in response to the enable signal.
 6. Themulti-chip package system of claim 5, wherein the termination controllerperforms the termination operation in response to an enable signal for apredetermined semiconductor chip among the plurality of semiconductorchips.
 7. The multi-chip package system of claim 5, wherein thetermination controller comprises: a detection unit suitable fordetecting whether the enable signal is activated or not and to output adetection signal; and an operation unit suitable for performing thetermination operation on the one transmission line in response to thedetection signal. 8-16. (canceled)